module cunterN2 (clk,rst,sel,q1,q2);
		input clk;
		input rst;
		input sel;
		
		output reg [3:0] q1;
		output reg q2;
		
		
		wire [3:0] N;
		
		parameter N1=4'd10;
		parameter N2=4'd6;
		
		assign N=(sel)?N1:N2;
		
		always @(posedge clk or posedge rst)
			begin
				if (rst) begin
					q1<=4'd0;
					q2<=1'b0;
					end
				else
					if (q1<N-1) begin
						q1<=q1+1'b1;
						q2<=1'b0;
						end
						else begin
							q1<=4'd0;
							q2<=1'b1;
							end
			 end
endmodule